INTRODUCTION
having made the T flip flop its now time to make asynchronous counter using t ff . If u have not made T flip flop then move back to the T flip flop .
T flip flop can be used to make the asynchronous counter .
WHAT DO YOU MEAN BY ASYNCHRONOUS ?
Asynchcronous means event which are not co-ordinated at the same time . Asynchronus does not mean that the circuit does not have clock . It means that the clock's are not sychoroised i.e event occuring are not occuring under the same clock .
HOW ?
as you can see in the truth table that the T flip flop retains the state when T='0' and the T flip flop toggels its state when T='1' .
TEST BENCH WAVEFORM
NOTE
DO NOT FORGET TO ADD SOURCE OF THE T FLIP FLOP YOU HAVE MADE .
having made the T flip flop its now time to make asynchronous counter using t ff . If u have not made T flip flop then move back to the T flip flop .
T flip flop can be used to make the asynchronous counter .
WHAT DO YOU MEAN BY ASYNCHRONOUS ?
Asynchcronous means event which are not co-ordinated at the same time . Asynchronus does not mean that the circuit does not have clock . It means that the clock's are not sychoroised i.e event occuring are not occuring under the same clock .
HOW ?
the binary representation of the digits are shown in the figure . The binary equivalent consists of 4 bits , B3 ,B2 , B1 ,B0 .leftmost being the MSB and the rightmost being the LSB .
B0 toggles whenever the clock occurs .
The B1 toggels (changes state) when the B0 toggles .
B2 toggles when the B1 and B0 both toggles .
similarly B2 toggles when B2 ,B1 and B0 toggles .
VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity async is
Port ( t1 : in STD_LOGIC;
clk1 : in STD_LOGIC;
a : inout STD_LOGIC;
b : inout STD_LOGIC;
c : inout STD_LOGIC ;
q1 : inout STD_LOGIC;
pr1: in STD_LOGIC;
cr1: in STD_LOGIC;
qbar1 : inout STD_LOGIC);
end async;
architecture Behavioral of async is
component t_ff4 is
Port ( t : in STD_LOGIC;
clk : in STD_LOGIC;
pr: in STD_LOGIC;
cr: in STD_LOGIC;
q : inout STD_LOGIC;
qbar : inout STD_LOGIC);
end component;
signal abar,bbar,cbar:STD_LOGIC;
begin
tff1: t_ff4 port map (t1,clk1,pr1,cr1,a,abar);
tff2: t_ff4 port map (t1,a,pr1,cr1,b,bbar);
tff3: t_ff4 port map (t1,b,pr1,cr1,c,cbar);
tff4: t_ff4 port map (t1,c,pr1,cr1,q1,qbar1);
end Behavioral;
RTL SCHEMATIC
NOTE
DO NOT FORGET TO ADD SOURCE OF THE T FLIP FLOP YOU HAVE MADE .
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